1. Field of Invention
The invention relates to a driving circuit for a display device, and, in particular, to a driving circuit supplying a target voltage signal to a capacitance load of a display device. More specifically, the invention relates to a display driving circuit applying a voltage corresponding to a pixel information signal across a row electrode in a display device such as a liquid crystal display panel. The invention also relates to a display device using the driving circuit.
2. Related Art
FIG. 1 is a circuit diagram showing an aspect of a driving circuit used in a conventional liquid crystal display device.
The aspect of the driving circuit of FIG. 1 supplies a driving voltage signal of corresponding pixel information to a source bus coupled to a row electrode of a liquid crystal display device, such as a source electrode of a thin film transistor (TFT) of an active device, which drives a pixel and extends along a first axis of a frame region. For example, each source bus can be provided with one driving circuit.
The driving circuit includes a grayscale voltage generating circuit 10 supplying digital pixel data serving as the pixel information signal, an amplifier 20 having an input coupled to an output of the grayscale voltage generating circuit 10, and a switch 30 controlling the power of the amplifier 20 (i.e., the ON/OFF of the bias current). The output of the amplifier 20 is connected to the source bus through an output line 40.
The grayscale voltage generating circuit 10 disposed in a primary stage comprises digital-to-analog converters and serves as a driving signal supply mechanism supplying a driving signal of a target voltage. The grayscale voltage generating circuit 10 has a voltage-dividing circuit formed by a plurality of resistor elements connected in series. As shown, the voltage-dividing circuit has one end coupled to a positive side power voltage Vdd and the other end coupled to a negative side power voltage Vss. The voltage-dividing circuit divides the voltage between Vdd and Vss, and thus generates a plurality of ascending or descending grayscale voltages. Common connection points between the resistor elements are respectively connected to first ends of switch elements, and second ends of the switch elements are connected together and serve as an output terminal of the grayscale voltage generating circuit 10. The switch elements can be individually controlled to be ON according to the input pixel data Vdata. Thus, among various grayscale voltages formed by the voltage-dividing circuit, only the grayscale voltage, which corresponds to the switch element turned on according to the pixel data Vdata, can be output as the driving signal Vin.
The amplifier 20 disposed in the secondary stage includes complementarily connected n-channel and p-channel field effect transistors (FET) 21 and 22 having gates to commonly receive the driving signal Vin, and a constant current source 23 having one end connected to a source of the n-channel FET 21. The p-channel FET 22 has a drain connected to the positive side power voltage Vdd. The other end of the constant current source 23 is coupled to one end of the switch element 30. The other end of the switch element 30 is connected to the negative side power voltage Vss. The switch element 30 is controlled to be ON/OFF according to a control signal C0 of the control circuit (not shown). A closed loop is formed between positive and negative power voltages of the amplifier 20 only when the switch element 30 is ON. The output current of the constant current source 23 serves as a bias current, and the amplifier 20 has a driving ability corresponding to the bias current necessary to achieve the amplifying effect. That is, the amplifier 20 outputs the driving signal Vin corresponding to the input according to a passing rate corresponding to the inherent bias current of the constant current source 23. The source of the p-channel FET 22 and the drain of the n-channel FET 21 are connected together, and the common connection portion serves as the output terminal of the amplifier, connected to the output line 40 or the source bus.
The source bus regulates the potential of the source electrode of the TFT formed in the display region. For example, when the column selection signal (or the wire selection signal, the gate control signal) in the gate bus of the column electrode, which crosses the source bus and extends along a second axis of the frame region, enables the TFT to be ON, the supplied potential of the driving voltage signal is applied to the liquid crystal part in the liquid crystal layer from the pixel electrode coupled to the drain electrode in the TFT. On an opposite side of the pixel electrode, a common electrode 50 clamping the liquid crystal layer and substantially crossing over the full region of the frame is provided. The liquid crystal part changes the molecule orientation and thus the optical modulation state thereof according to the voltage generated between the pixel electrode and the common electrode 50. In this aspect, the source bus extends greatly in the frame region, and the capacitor Ccol located between the output line 40 and the common electrode 50 may be regarded as an equivalent capacitor of the source bus and the liquid crystal layer.
FIG. 2 shows operation of the driving circuit, wherein the topmost stage represents the waveform of the driving signal Vin, the secondary stage represents the waveform of the horizontal sync signal of the timing signal of the pixel data Vdata, the third stage represents the waveform of the output voltage Vout of the amplifier 20, and the fourth stage represents the waveform of the amplifier 20 according to the bias current of the constant current source 23, and the bottommost stage represents the waveform of the switch control signal C0.
The horizontal sync signal can be used to regulate the update timing of the pixel data Vdata. In this example, one horizontal scan period (the one scan line) is divided according to the time of the horizontal sync signal falling to the low level. Thus, the starting period and the ending period of the column are displayed according to the time, and the pixel data Vdata is updated in each column.
Conditions under which the horizontal scan period of the pixel data Vdata is shifted to the (n−1)th column, the nth column, the (n+1)th column, and the (n+2)th column are detailed as follows.
In the nth column, the grayscale voltage generating circuit 10 generates the grayscale voltage (i.e., the driving signal Vin) corresponding to the pixel data Vdata in response to the drop of the horizontal sync signal. At this time, any switch in the circuit 10 is ON corresponding to the data. Next, when the horizontal sync signal rises, the control signal C0 of the switch 30 becomes the high level and is held high in the entire fixed period TA. The switch 30 is ON when the control signal C0 is at the high level. Thus, the constant current source 23 can output the current in the entire fixed period TA to provide the power to the complementary transistors 21 and 22 according to the bias current of the constant current source 23. The value of the bias current is the inherent fixed current value Ia of the constant current source 23. Thus, the output Vout of the amplifier 20 slowly approaches the value of the driving signal Vin serving as the target value in the entire fixed period TA at the passing rate regulated by the bias current value Ia. In this example, the value of Vin of the (n−1)th column is the minimum, and the value of Vin of the nth column is the maximum. It is possible to set the bias current value Ia and the period TA in advance such that the output Vout can be changed according to the maximum variation (maximum output amplitude) Vpp from the minimum to the maximum of Vin.
Next, in the (n+1)th column, the grayscale voltage generating circuit 10 generates the driving signal Vin corresponding to the pixel data Vdata in response to the drop of the horizontal sync signal. Also, the control signal C0 of the switch 30 ascends to the high level and is kept high in the entire fixed period TA in response to the rise of the horizontal sync signal, and the switch 30 and constant current source 23 are controlled. In this example, however, the value of Vin of the (n+1)th column becomes an intermediate value, and the output Vout can reach the target value of Vin in the middle of the period TA but not the end of the period.
In addition, grayscale voltage generating circuit 10, switch 30, and constant current source 23 similarly operate in the (n+2)th column. In this example, however, the value of Vin of the (n÷2)th column is the same as the intermediate value of the previous column. In the period TA, the input will not be changed even if the bias current is applied to the complementary transistors 21 and 22, so the output Vout will not be changed.
Accordingly, target voltage is achieved by the beginning or middle of the bias period TA, in addition to the request on the column of the maximum output amplitude Vpp, a condition disadvantageous to power conservation after the target voltage is reached, since bias currents of the amplifier transistors 21 and 22 are not utilized.